This invention relates to digital filters and, more particularly, to wave digital filters.
The wave digital filter, which is a large family of digital filter structures, has recently been the subject of increased practical investigation due to its many useful properties, such as low coefficient sensitivity which allows for a significant hardware savings.
In addition, the digital wave filter structure can be realized completely free of both large scale oscillations (overflow oscillations) and granularity oscillations (limit cycles) thereby eliminating the need to protect against overflows and saving hardware.
The wave digital filter is derived from a so-called reference filter, such as a classical ladder or lattice structure. The ladder structure has received a great deal of attention in the literature such as in the following articles: "Design of Wave Digital Filters for Communications Applications," by A. Fettweis, G. J. Mandeville and C-Y Kao, Proc. of IEEE International Symposium on Circuits and Systems, pp. 162-165, April, 1975; "Suppression of Parasitic Oscillations in Wave Digital Filters", by A. Fettweis and K. Meerkotter, IEEE Trans. Circuits and Systems, Vol. CAS-22, No. 3, pp. 239-246, March 1975; and "Suppression of Parasitic Oscillations in Half-Synchronic Wave Digital Filters", by A. Fettweis and K. Meerkotter, IEEE Trans. Circuits and Systems, Vol. CAS-23, No. 2, pp. 126-126, February, 1976. The wave digital filter derived from LC ladders, however, has some hardware disadvantages. Such filters are typically realized as cascaded parallel and series 3-port adapters wherein 3-port adapters are special purpose arithmetic units comprised of one or two binary multipliers and four binary adders. Although adapters of the same type have identical signal flow graphs, their location in the filter influences their hardware structure. Thus, each adapter must be uniquely realized so as to compensate for the buildup of computational delays in the ladder structure. Although it is possible to realize ladder filters without computational delay buildup by deriving them from a reference filter of cascaded unit elements (see, for example, "Digital Filter Structures Related to Classical Filter Networks", by A. Fettweis, Arch. Elektr. Ubertrag. 25, 1971, pp. 79-89), such a structure only allows for transmission zeros at zero and one-half the sampling frequency which limits the application of the structure. Another disadvantage of ladder structures is that the number of delays (or storage elements) is greater than the degree of the transfer function of the filter, i.e., the ladder structures are not canonic in delays. In "Canonic Realization of Ladder Wave Digital Filters", by A. Fettweis, Int. Journal of Circuit Theory and App., Vol. 3, December 1975, pp. 321-332, a modification is suggested such that ladders can be made canonic in delays. This modified approach, however, requires additional adders.
The wave digital filter derived from a symmetric lattice is canonic in delays with no additional hardware required. Furthermore, this structure can be realized without computational delay buildup. Thus, it can be realized as cascaded unit elements without restrictions on the transmission zeros. This results in all adapters (arithmetic units) being identical in structure. Such an arithmetic unit can be integrated and together with storage elements used as building block for digital filters. The lattice wave digital filter is discussed in "Wave Digital Lattice Filters" by A. Fettweis, H. Levin and A. Sedlmeyer, Int. Journal on Circuit Theory and App., Vol. 2, June 1974, pp. 203-211.
An object of this invention is to realize a lattice wave digital filter having a minimum number of arithmetic units and, in particular, to minimize the number of arithmetic multipliers required in the filter realization.